1. Field
One or more embodiments herein relate to semiconductor memory devices.
2. Description of the Related Art
Some semiconductor memory devices have used a clock signal as a reference signal to synchronize operational timing. When an external clock signal is used, a time delay (e.g., clock skew) may occur. Various options have been considered in an attempt to control the time delay, in order to make an internal clock signal of the semiconductor memory device have the same phase as the external clock signal.
Especially, in the case of a double data rate synchronous dynamic random access memory (DDR SDRAM), synchronous operation of the clock may be of interest when applying a read latency operation and an on-die termination (ODT) technology. Consequently, a timing control circuit may be built into the DDR SDRAM for this purpose.
As the operational speeds of synchronous semiconductor memory devices increase, use of a delay locked loop (DLL) circuit having a robust jitter characteristic may serve as one option for timing control. However, in many cases, DLL circuits have been shown to consume too much power, which may adversely affect the overall performance of the semiconductor device.